RISC-V Processor ASIC
With a partner, I built a 3-stage pipelined RV32I processor in SystemVerilog: fetch, a combined decode/execute stage, and a combined memory/writeback stage, with register-file bypassing and writeback-to-execute forwarding. The write-back, write-allocate caches are built from Skywater 130nm SRAM macros. We took the design through the full RTL-to-GDS flow (VCS, Design Compiler, and Innovus via Hammer), closed setup and hold timing after place-and-route, and ran the full test suite against the routed netlist.
I owned the optimization against the competition's energy × area figure of merit, trying 3-, 4-, and 5-stage pipelines, a branch predictor, set-associative and direct-mapped caches at several sizes, and different SRAM placements. The 5-stage pipeline gained about 10 MHz but lost more than that in extra cycles. The 64-entry branch predictor nearly doubled core power for only a small drop in cycle count, so I cut it. Small 1 kB direct-mapped caches beat both the larger caches and the set-associative ones. Clock-gating the datapath and caches and relaxing the clock to about 24 MHz brought the core to 3.8 mW in 0.86 mm², which took the figure of merit from about 10 to 42.2 and made the design an Apple Design Project finalist.